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Hi all,
On github I see in https://github.com/Avnet/hdl/blob/master/Projects/fmchc_python1300c/zedboard_fmchc_python1300c.xdc that the camera clock is defined as 54 MHz (period=3.703ns). I do not quite understand where this value comes from. The datasheet states the Master clock should be 72 MHz.
And when I try to set input delay constraints I can only get over 50 MHz without timing violations if I select a -3 speed for the Zynq which the Zedboard does not have.
Can anyone shed some light on this?
Maarten


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